The present invention relates to an information processing apparatus, a debugging unit and a debugging method of the information processing apparatus.
In an example described in Patent Literature 1 (JP 2006-252006A), a 1-pin external terminal is used for interface between an external tool (host device) and a debugging unit with a microcontroller (MCU) built therein by use of asynchronous communication unit (UART: universal asynchronous receiver-transmitter). A transmission/reception instruction is issued from a CPU (central processing unit) to the asynchronous communication unit, and an operation clock signal of the asynchronous communication unit is supplied from a clock oscillator. This clock signal is also supplied to the CPU.
Accordingly, when the microcontroller changes to a low power consumption mode to stop the clock signal, the asynchronous communication unit is also stopped to disable communication with the external tool, resulting in that a debugging operation is interrupted.
Patent Literature 2 (Japanese patent No. 4145146) discloses a technique of using a background debug system for interface between an external tool (host unit) and a debugging unit with a microcontroller (MCU) built therein. In the debugging unit with the microcontroller, a 1-pin external terminal is used to interface with the external tool. The background debug system can operate independently from a CPU. An operation clock is supplied by a dedicated background debug clock signal from a clock unit. When activation of the background debug system is notified to the clock unit by an EN_BDM signal, the supply of the background debug clock signal is not stopped even if supply of clock signal to the CPU or the like is stopped. The technique disclosed in Patent Literature 2 is largely different from the technique disclosed in Patent Literature 1 in this point.
Patent Literature 2 further discloses a method of synchronizing a communication rate between the background debug system to which a frequency-divided clock signal is supplied from a clock control section having a function of frequency-dividing a clock signal, and the external tool. A communication rate synchronizing procedure is as follows. First, the external tool outputs a synchronizing request. When detecting the synchronizing request, the background debug system outputs an “L” pulse having a width of a predetermined number of clocks (128 cycles) in response to the request. The external tool can recognize a clock rate of the background debug clock signal used by the background debug system by measuring the width (time) of the “L” pulse. The external tool performs communication at the same clock rate as the clock rate of the background debug clock. In this manner, the communication rate can be synchronized.
As described above, when the background debug system is activated, the background debug clock is not stopped even if the microcontroller (MCU) stops its clock signal and shifts to the low power consumption mode. Thus, the microcontroller can communicate with the external tool at all times, thereby continuing the debug operation. However, according to a general method of shifting the microcontroller to the low power consumption mode, a frequency dividing ratio of the clock control section is often changed according to a user application program to be debugged. Accordingly, when the microcontroller (MCU) shifts to the low-speed clock mode, that is, when low power consumption mode and the clock control section and the oscillator are provided in common, a switching point of the clock rate of the background debug clock signal is generally unrelated to a state of communication between the background debug system and the external tool, and the communication rate may asynchronously change, which conducts to improper communication. In other words, the debug operation cannot be normally continued.
Patent Literature 2 discloses the method of synchronizing the communication rate between the background debug system and the external tool. However, according to the communication rate synchronizing method, since the synchronizing procedure is started in response to the synchronizing request from the external tool, the external tool cannot change the communication rate at a proper timing even when the frequency dividing ratio of the clock control section is changed during the debug operation, in particular, during communication. Therefore, since the external tool has no means and methods for detecting timing of changing the clock rate of the background debug clock signal, it is impossible to avoid the above-mentioned improper communication.